The present invention relates to a method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having an N channel type field effect transistor and a P channel type field effect transistor, and the memory array part also having an N channel type field effect transistor and a P channel type field effect transistor.
Attendant on the progress of miniaturization of semiconductor integrated circuits, it has been becoming difficult to enhance the performance of the field effect transistor by only the scaling adopted in the past. In view of this, a technology of enhancing the performance by increasing the mobility through the use of a film stress has been paid attention to in relation to the semiconductor integrated circuits of the 90 nm generation and the latter generations (see, for example, Shinya Ito, et al., “Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design”, 2001 IEDM, or K. Goto, et al., “High Performance 35 nm Gate CMOSFET's with Vertical Scaling and Total Stress Control for 65 nm Technology”, 2003 IEDM). In this technology, insulation films different in film stress are formed on the respective regions of an N channel type field effect transistor (hereinafter referred to as N-type FET) and a P channel type field effect transistor (hereinafter referred to as P-type FET) after the formation of gate parts, channel forming regions and source/drain regions. Specifically, an insulation film having a tensile stress is formed on the region of the N-type FET, and an insulation film having a compressive stress is formed on the region of the P-type FET.
In a semiconductor integrated circuit, a logic part having N-type FETs and P-type FETs and a memory array part having N-type FETs and P-type FETs are usually produced on the basis of the same step. Now, a method of manufacturing a memory array part composed of an SRAM (Static Random Access Memory) according to the related art (for convenience, referred to as the first manufacturing method according to the related art) will be described referring to FIGS. 40A, 40B, 40C, 41A, 41B, 41C, 42A, 42B, 42C, 43A and 43B, which are schematic partly end elevation diagrams of a semiconductor substrate and the like. The schematic partly end elevation diagrams in these drawings or schematic partly end elevation diagrams in various drawings which are schematic partly end elevation diagrams of a semiconductor substrate and the like to be described later are schematic partly end elevation diagrams taken along the dot-dash line in FIG. 1C. Besides, an equivalent circuit of the memory array part is shown in FIG. 1B, and a schematic layout diagram of a gate part, source/drain regions and the like is shown in FIG. 1C and FIG. 10B.
[Step 10]
First, based on a known method, a device separation region 11 having a trench structure is formed in a semiconductor substrate 10, then a gate part composed of a gate insulation film 21, a gate electrode 22 and an offset film 23 is formed on the semiconductor substrate 10, gate side walls 24 are formed on side surfaces of the gate part, and source-drain regions 25 are formed in the semiconductor substrate 10. Incidentally, the region, interposed between the two source/drain regions 25, of the semiconductor substrate 10 corresponds to a channel forming region. In this manner, P-type FETs 220A (see TR1 and TR4 in FIGS. 1B and 1C) and N-type FETs 220B (see TR2, TE3, TR5 and TR6 in FIGS. 1B and 1C) can be obtained (see FIG. 40A).
[Step 11]
Next, for example, based on a plasma CVD process, a first insulation film 31 composed of a 50 nm thick silicon nitride film and having a tensile stress is formed on the whole surface (see FIG. 40B), and a second insulation film 32 composed of a 30 nm thick silicon oxide film is formed on the first insulation film 31 (see FIG. 40C).
[Step 12]
Thereafter, based on the known lithographic technology, a resist layer 236A covering the region of the N-type FETs 220B is formed (see FIG. 41A), then the second insulation film 32 and the first insulation film 31 exposed in the region of the P-type FETs 220A not covered with the resist layer 236A are removed by a dry etching process (see FIG. 41B), and the resist layer 236A is removed based on an ashing treatment (see FIG. 41C).
[Step 13]
Next, for example, based on a plasma CVD process, a third insulation film 33 composed of a 50 nm thick silicon nitride film and having a compressive stress is formed on the whole surface (see FIG. 42A). Thereafter, based on the known lithographic technology, a resist layer 236B covering the region of the P-type FETs 220A is formed (see FIG. 42B), then the third insulation film 33 exposed in the region of the N-type FETs 220B not covered with the resist layer 236B is removed by a dry etching process (see FIG. 42C), and the resist layer 236B is removed based on an ashing treatment (see FIG. 43A). Since the second insulation film 32 composed of the silicon oxide film is formed as an etching stopper layer, the third insulation film 33 can be securely removed by the dry etching process. Incidentally, at the time of removing the third insulation film 33, the third insulation film 33 is dry etched in such a manner as to obtain a three-layer structure of the first insulation film 31, the second insulation film 32, and the third insulation film 33 and that the semiconductor substrate 10 and the like are not exposed in the boundary region between the first insulation film 31 and the third insulation film 33.
[Step 14]
Thereafter, a layer insulation layer 34 and a resist layer 236C are formed on the whole surface, and the layer insulation layer 34 is dry etched by using the resist layer 236C as an etching mask, to form openings 34A for forming contact holes and an opening 34B for forming a local inter connect 35 (see the schematic layout diagram in FIG. 10B) in the layer insulation layer 34 (see FIG. 43B), and the resist layer 236C is removed. Next, a wiring material layer is formed on the layer insulation layer 34 inclusive of the inside of the openings 34A and 34B, and the wiring material layer on the layer insulation layer 34 is patterned, whereby a wiring layer can be formed on the layer insulation layer 34 and, simultaneously, the contact holes and the local interconnect 35 can be formed.
Alternatively, another method of producing a memory array part according to the related art (for convenience, referred to as the second manufacturing method according to the related art) may be adopted, which will be described referring to FIGS. 44A, 44B, 44C, 45A, 45B, and 45C, which are schematic partly end elevation diagrams of a semiconductor substrate and the like.
[Step 20]
First, based on a known method, a device separation region 11 having a trench structure is formed in a semiconductor substrate 10, then a gate part composed of a gate insulation film 21, a gate electrode 22 and an offset film 23 is formed on the semiconductor substrate 10, thereafter gate side walls 24 are formed on side surfaces of the gate part, and source/drain regions 25 are formed in the semiconductor substrate 10. Incidentally, the region, between the two source/drain regions 25, of the semiconductor substrate 10 corresponds to a channel forming region. In this manner, P-type FETs 320A (see TR1 and TR4 in FIGS. 1B and 1C) and N-type FETs 320B (see TR2, TR3, TR5, and TR6 in FIGS. 1B and 1C) can be obtained.
[Step 21]
Next, for example based on a plasma CVD process, a first insulation film 31 composed of a 50 nm thick silicon nitride film and having a tensile stress is formed on the whole surface. Thereafter, based on a known lithographic technology, a resist layer 336A covering the region of the N-type FETs 320B is formed (see FIG. 44A), the first insulation film 31 exposed in the region of the P-type FETs 320A not covered with the resist layer 336A is removed by a dry etching process (see FIG. 44B), and the resist layer 336A is removed based on an ashing treatment (see FIG. 44C).
[Step 22]
Next, for example, based on a plasma CVD process, a third insulation film 33 composed of a 50 nm thick silicon nitride film and having a compressive stress is formed on the whole surface (see FIG. 45A). Thereafter, based on a known lithographic technology, a resist layer 336B covering the region of the P-type FETs 320A is formed (see FIG. 45B), and ion implantation for relaxation of compressive stress is applied to the third insulation film 33 exposed in the region of the N-type FETs 320B not covered with the resist layer 336B. Examples of the ion species used here include germanium (Ge). Thereafter, the resist layer 336B is removed based on an ashing treatment.
[Step 23]
Next, a layer insulation layer 34 and a resist layer 336C are formed on the whole surface, the layer insulation layer 34 is dry etched by using the resist layer 336C as an etching mask, to form openings 34A for forming contact holes and an opening 34B for forming a local interconnect 35 (see the schematic layout diagram in FIG. 10B) in the layer insulation layer 34 (see FIG. 45C), and the resist layer 336C is removed. Subsequently, a wiring material layer is formed on the layer insulation layer 34 inclusive of the inside of the openings 34A and 34B, and the wiring material layer on the layer insulation layer 34 is patterned, whereby a wiring layer can be formed on the layer insulation layer 34 and, simultaneously, the contact holes and the local interconnect 35 can be formed.